172 related articles for article (PubMed ID: 16510939)
1. Architectures for high-performance FPGA implementations of neural models.
Weinstein RK; Lee RH
J Neural Eng; 2006 Mar; 3(1):21-34. PubMed ID: 16510939
[TBL] [Abstract][Full Text] [Related]
2. Methodology and design flow for assisted neural-model implementations in FPGAs.
Weinstein RK; Reid MS; Lee RH
IEEE Trans Neural Syst Rehabil Eng; 2007 Mar; 15(1):83-93. PubMed ID: 17436880
[TBL] [Abstract][Full Text] [Related]
3. FPNA: interaction between FPGA and neural computation.
Girau B
Int J Neural Syst; 2000 Jun; 10(3):243-59. PubMed ID: 11011795
[TBL] [Abstract][Full Text] [Related]
4. The impact of arithmetic representation on implementing MLP-BP on FPGAs: a study.
Savich AW; Moussa M; Areibi S
IEEE Trans Neural Netw; 2007 Jan; 18(1):240-52. PubMed ID: 17278475
[TBL] [Abstract][Full Text] [Related]
5. Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler.
Minkovich K; Srinivasa N; Cruz-Albrecht JM; Cho Y; Nogin A
IEEE Trans Neural Netw Learn Syst; 2012 Jun; 23(6):889-901. PubMed ID: 24806761
[TBL] [Abstract][Full Text] [Related]
6. Feedforward neural network implementation in FPGA using layer multiplexing for effective resource utilization.
Himavathi S; Anitha D; Muthuramalingam A
IEEE Trans Neural Netw; 2007 May; 18(3):880-8. PubMed ID: 17526352
[TBL] [Abstract][Full Text] [Related]
7. An FPGA hardware/software co-design towards evolvable spiking neural networks for robotics application.
Johnston SP; Prasad G; Maguire L; McGinnity TM
Int J Neural Syst; 2010 Dec; 20(6):447-61. PubMed ID: 21117269
[TBL] [Abstract][Full Text] [Related]
8. Event management for large scale event-driven digital hardware spiking neural networks.
Caron LC; D'Haene M; Mailhot F; Schrauwen B; Rouat J
Neural Netw; 2013 Sep; 45():83-93. PubMed ID: 23522624
[TBL] [Abstract][Full Text] [Related]
9. Real-time neural network inversion on the SRC-6e reconfigurable computer.
Duren RW; Marks RJ; Reynolds PD; Trumbo ML
IEEE Trans Neural Netw; 2007 May; 18(3):889-901. PubMed ID: 17526353
[TBL] [Abstract][Full Text] [Related]
10. Comparison of GPU- and CPU-implementations of mean-firing rate neural networks on parallel hardware.
Dinkelbach HÜ; Vitay J; Beuth F; Hamker FH
Network; 2012; 23(4):212-36. PubMed ID: 23140422
[TBL] [Abstract][Full Text] [Related]
11. An FPGA-based approach to high-speed simulation of conductance-based neuron models.
Graas EL; Brown EA; Lee RH
Neuroinformatics; 2004; 2(4):417-36. PubMed ID: 15800372
[TBL] [Abstract][Full Text] [Related]
12. Real-time simulation of large-scale neural architectures for visual features computation based on GPU.
Chessa M; Bianchi V; Zampetti M; Sabatini SP; Solari F
Network; 2012; 23(4):272-91. PubMed ID: 23116085
[TBL] [Abstract][Full Text] [Related]
13. FHAST: FPGA-Based Acceleration of Bowtie in Hardware.
Fernandez EB; Villarreal J; Lonardi S; Najjar WA
IEEE/ACM Trans Comput Biol Bioinform; 2015; 12(5):973-81. PubMed ID: 26451812
[TBL] [Abstract][Full Text] [Related]
14. Real-time data analysis for medical diagnosis using FPGA-accelerated neural networks.
Sanaullah A; Yang C; Alexeev Y; Yoshii K; Herbordt MC
BMC Bioinformatics; 2018 Dec; 19(Suppl 18):490. PubMed ID: 30577751
[TBL] [Abstract][Full Text] [Related]
15. Parallel field programmable gate array particle filtering architecture for real-time neural signal processing.
Mountney J; Silage D; Obeid I
Annu Int Conf IEEE Eng Med Biol Soc; 2010; 2010():2674-7. PubMed ID: 21096196
[TBL] [Abstract][Full Text] [Related]
16. A component-based FPGA design framework for neuronal ion channel dynamics simulations.
Mak TS; Rachmuth G; Lam KP; Poon CS
IEEE Trans Neural Syst Rehabil Eng; 2006 Dec; 14(4):410-8. PubMed ID: 17190033
[TBL] [Abstract][Full Text] [Related]
17. The application of an Actel field programmable gate array in the design of an ECG RR interval recorder.
Harrison A; Hayes-Gill BR; Crowe JA; Chang ST
J Med Eng Technol; 1995; 19(6):198-204. PubMed ID: 8742867
[TBL] [Abstract][Full Text] [Related]
18. The role of the asymptotic dynamics in the design of FPGA-based hardware implementations of gIF-type neural networks.
Rostro-Gonzalez H; Cessac B; Girau B; Torres-Huitzil C
J Physiol Paris; 2011; 105(1-3):91-7. PubMed ID: 21964248
[TBL] [Abstract][Full Text] [Related]
19. Hardware implementation of stochastic spiking neural networks.
Rosselló JL; Canals V; Morro A; Oliver A
Int J Neural Syst; 2012 Aug; 22(4):1250014. PubMed ID: 22830964
[TBL] [Abstract][Full Text] [Related]
20. Wearable FPGA based wireless sensor platform.
Ahola T; Korpinen P; Rakkola J; Rämö T; Salminen J; Savolainen J
Annu Int Conf IEEE Eng Med Biol Soc; 2007; 2007():2288-91. PubMed ID: 18002448
[TBL] [Abstract][Full Text] [Related]
[Next] [New Search]
