BIOMARKERS

Molecular Biopsy of Human Tumors

- a resource for Precision Medicine *

172 related articles for article (PubMed ID: 16510939)

  • 21. Performance/price estimates for cortex-scale hardware: a design space exploration.
    Zaveri MS; Hammerstrom D
    Neural Netw; 2011 Apr; 24(3):291-304. PubMed ID: 21232918
    [TBL] [Abstract][Full Text] [Related]  

  • 22. Streaming parallel GPU acceleration of large-scale filter-based spiking neural networks.
    Slażyński L; Bohte S
    Network; 2012; 23(4):183-211. PubMed ID: 23098420
    [TBL] [Abstract][Full Text] [Related]  

  • 23. System-on-chip design for ultrasonic target detection using split-spectrum processing and neural networks.
    Saniie J; Oruklu E; Yoon S
    IEEE Trans Ultrason Ferroelectr Freq Control; 2012 Jul; 59(7):1354-68. PubMed ID: 22828831
    [TBL] [Abstract][Full Text] [Related]  

  • 24. High-performance reconfigurable hardware architecture for restricted Boltzmann machines.
    Ly DL; Chow P
    IEEE Trans Neural Netw; 2010 Nov; 21(11):1780-92. PubMed ID: 20858578
    [TBL] [Abstract][Full Text] [Related]  

  • 25. [Thalamocortical Neural Mass Model Simulation and Study Based on Field Programmable Gate Array].
    Liang Z; Zhou J; Li X
    Sheng Wu Yi Xue Gong Cheng Xue Za Zhi; 2016 Aug; 33(4):616-25. PubMed ID: 29714455
    [TBL] [Abstract][Full Text] [Related]  

  • 26. Field-programmable gate array implementation of a probabilistic neural network for motor cortical decoding in rats.
    Zhou F; Liu J; Yu Y; Tian X; Liu H; Hao Y; Zhang S; Chen W; Dai J; Zheng X
    J Neurosci Methods; 2010 Jan; 185(2):299-306. PubMed ID: 19879294
    [TBL] [Abstract][Full Text] [Related]  

  • 27. Implementing spiking neural networks for real-time signal-processing and control applications: a model-validated FPGA approach.
    Pearson MJ; Pipe AG; Mitchinson B; Gurney K; Melhuish C; Gilhespy I; Nibouche M
    IEEE Trans Neural Netw; 2007 Sep; 18(5):1472-87. PubMed ID: 18220195
    [TBL] [Abstract][Full Text] [Related]  

  • 28. A new realization of time-to-digital converters based on FPGA internal routing resources.
    Wang H; Zhang M; Yao Q
    IEEE Trans Ultrason Ferroelectr Freq Control; 2013 Sep; 60(9):1787-95. PubMed ID: 24658711
    [TBL] [Abstract][Full Text] [Related]  

  • 29. A single FPGA-based portable ultrasound imaging system for point-of-care applications.
    Kim GD; Yoon C; Kye SB; Lee Y; Kang J; Yoo Y; Song TK
    IEEE Trans Ultrason Ferroelectr Freq Control; 2012 Jul; 59(7):1386-94. PubMed ID: 22828834
    [TBL] [Abstract][Full Text] [Related]  

  • 30. Simulating spiking neural networks on GPU.
    Brette R; Goodman DF
    Network; 2012; 23(4):167-82. PubMed ID: 23067314
    [TBL] [Abstract][Full Text] [Related]  

  • 31. Neural learning circuits utilizing nano-crystalline silicon transistors and memristors.
    Cantley KD; Subramaniam A; Stiegler HJ; Chapman RA; Vogel EM
    IEEE Trans Neural Netw Learn Syst; 2012 Apr; 23(4):565-73. PubMed ID: 24805040
    [TBL] [Abstract][Full Text] [Related]  

  • 32. An interval type-2 neural fuzzy chip with on-chip incremental learning ability for time-varying data sequence prediction and system control.
    Juang CF; Chen CY
    IEEE Trans Neural Netw Learn Syst; 2014 Jan; 25(1):216-28. PubMed ID: 24806655
    [TBL] [Abstract][Full Text] [Related]  

  • 33. Optimization and implementation of scaling-free CORDIC-based direct digital frequency synthesizer for body care area network systems.
    Juang YS; Ko LT; Chen JE; Sung TY; Hsin HC
    Comput Math Methods Med; 2012; 2012():651564. PubMed ID: 23251230
    [TBL] [Abstract][Full Text] [Related]  

  • 34. An FPGA-based ultrasound imaging system using capacitive micromachined ultrasonic transducers.
    Wong LL; Chen AI; Logan AS; Yeow JT
    IEEE Trans Ultrason Ferroelectr Freq Control; 2012 Jul; 59(7):1513-20. PubMed ID: 22828846
    [TBL] [Abstract][Full Text] [Related]  

  • 35. Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network.
    Shah N; Chaudhari P; Varghese K
    IEEE Trans Neural Netw Learn Syst; 2018 Dec; 29(12):5922-5934. PubMed ID: 29993989
    [TBL] [Abstract][Full Text] [Related]  

  • 36. Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs.
    Liu S; Fan H; Ferianc M; Niu X; Shi H; Luk W
    IEEE Trans Neural Netw Learn Syst; 2022 Aug; 33(8):3974-3987. PubMed ID: 33577458
    [TBL] [Abstract][Full Text] [Related]  

  • 37. HRLSim: a high performance spiking neural network simulator for GPGPU clusters.
    Minkovich K; Thibeault CM; O'Brien MJ; Nogin A; Cho Y; Srinivasa N
    IEEE Trans Neural Netw Learn Syst; 2014 Feb; 25(2):316-31. PubMed ID: 24807031
    [TBL] [Abstract][Full Text] [Related]  

  • 38. Optimization of Deep Neural Networks Using SoCs with OpenCL.
    Gadea-Gironés R; Colom-Palero R; Herrero-Bosch V
    Sensors (Basel); 2018 Apr; 18(5):. PubMed ID: 29710875
    [TBL] [Abstract][Full Text] [Related]  

  • 39. A survey on FPGA-based sensor systems: towards intelligent and reconfigurable low-power sensors for computer vision, control and signal processing.
    García GJ; Jara CA; Pomares J; Alabdo A; Poggi LM; Torres F
    Sensors (Basel); 2014 Mar; 14(4):6247-78. PubMed ID: 24691100
    [TBL] [Abstract][Full Text] [Related]  

  • 40. Asynchronous cellular automaton-based neuron: theoretical analysis and on-FPGA learning.
    Matsubara T; Torikai H
    IEEE Trans Neural Netw Learn Syst; 2013 May; 24(5):736-48. PubMed ID: 24808424
    [TBL] [Abstract][Full Text] [Related]  

    [Previous]   [Next]    [New Search]
    of 9.