These tools will no longer be maintained as of December 31, 2024. Archived website can be found here. PubMed4Hh GitHub repository can be found here. Contact NLM Customer Service if you have questions.


BIOMARKERS

Molecular Biopsy of Human Tumors

- a resource for Precision Medicine *

173 related articles for article (PubMed ID: 18255644)

  • 1. A parallel processing VLSI BAM engine.
    Hasan SR; Siong NK
    IEEE Trans Neural Netw; 1997; 8(2):424-36. PubMed ID: 18255644
    [TBL] [Abstract][Full Text] [Related]  

  • 2. A neural-network architecture for syntax analysis.
    Chen CH; Honavar V
    IEEE Trans Neural Netw; 1999; 10(1):94-114. PubMed ID: 18252507
    [TBL] [Abstract][Full Text] [Related]  

  • 3. A VLSI neural processor for image data compression using self-organization networks.
    Fang WC; Sheu BJ; Chen OC; Choi J
    IEEE Trans Neural Netw; 1992; 3(3):506-18. PubMed ID: 18276454
    [TBL] [Abstract][Full Text] [Related]  

  • 4. A CMOS analog adaptive BAM with on-chip learning and weight refreshing.
    Linares-Barranco B; Sanchez-Sinencio E; Rodriguez-Vazquez A; Huertas JL
    IEEE Trans Neural Netw; 1993; 4(3):445-55. PubMed ID: 18267748
    [TBL] [Abstract][Full Text] [Related]  

  • 5. IP core implementation of a self-organizing neural network.
    Hendry DC; Duncan AA; Lightowler N
    IEEE Trans Neural Netw; 2003; 14(5):1085-96. PubMed ID: 18244562
    [TBL] [Abstract][Full Text] [Related]  

  • 6. A programmable analog VLSI neural network processor for communication receivers.
    Choi J; Bang SH; Sheu BJ
    IEEE Trans Neural Netw; 1993; 4(3):484-95. PubMed ID: 18267752
    [TBL] [Abstract][Full Text] [Related]  

  • 7. A design of an associative memory array processor for ultrasonograph image acquisition and processing.
    Aly GM; el-Nadi NM; Fayed ZT; Faheem HM
    Biomed Sci Instrum; 2000; 36():283-8. PubMed ID: 10834246
    [TBL] [Abstract][Full Text] [Related]  

  • 8. Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.
    Abdelhalim K; Smolyakov V; Genov R
    IEEE Trans Biomed Circuits Syst; 2011 Oct; 5(5):430-8. PubMed ID: 23852175
    [TBL] [Abstract][Full Text] [Related]  

  • 9. Specification for a reconfigurable optoelectronic VLSI processor suitable for digital signal processing.
    Fey D; Kasche B; Burkert C; Tschäche O
    Appl Opt; 1998 Jan; 37(2):284-95. PubMed ID: 18268584
    [TBL] [Abstract][Full Text] [Related]  

  • 10. On VLSI Design of Rank-Order Filtering using DCRAM Architecture.
    Lin MC; Dung LR
    Integration (Amst); 2008 Feb; 41(2):193-209. PubMed ID: 19865599
    [TBL] [Abstract][Full Text] [Related]  

  • 11. Performance analysis and comparison of a minimum interconnections direct storage model with traditional neural bidirectional memories.
    Bhatti AA
    IET Nanobiotechnol; 2009 Dec; 3(4):81-102. PubMed ID: 19895156
    [TBL] [Abstract][Full Text] [Related]  

  • 12. NeuroPipe-Chip: A digital neuro-processor for spiking neural networks.
    Schoenauer T; Atasoy S; Mehrtash N; Klar H
    IEEE Trans Neural Netw; 2002; 13(1):205-13. PubMed ID: 18244419
    [TBL] [Abstract][Full Text] [Related]  

  • 13. Focal-plane processing architectures for real-time hyperspectral image processing.
    Chai SM; Gentile A; Lugo-Beauchamp WE; Fonseca J; Cruz-Rivera JL; Wills DS
    Appl Opt; 2000 Feb; 39(5):835-49. PubMed ID: 18337961
    [TBL] [Abstract][Full Text] [Related]  

  • 14. Optical content-addressable parallel processor: architecture, algorithms, and design concepts.
    Louri A
    Appl Opt; 1992 Jun; 31(17):3241-58. PubMed ID: 20725275
    [TBL] [Abstract][Full Text] [Related]  

  • 15. Designs and devices for optical bidirectional associative memories.
    Guest CC; Tekolste R
    Appl Opt; 1987 Dec; 26(23):5055-60. PubMed ID: 20523484
    [TBL] [Abstract][Full Text] [Related]  

  • 16. An analog VLSI recurrent neural network learning a continuous-time trajectory.
    Cauwenberghs G
    IEEE Trans Neural Netw; 1996; 7(2):346-61. PubMed ID: 18255589
    [TBL] [Abstract][Full Text] [Related]  

  • 17. Specification and implementation of a digital Hopfield-type associative memory with on-chip training.
    Johannet A; Personnaz L; Dreyfus G; Gascuel JD; Weinfeld M
    IEEE Trans Neural Netw; 1992; 3(4):529-39. PubMed ID: 18276455
    [TBL] [Abstract][Full Text] [Related]  

  • 18. Architecture and statistical model of a pulse-mode digital multilayer neural network.
    Kim YC; Shanblatt MA
    IEEE Trans Neural Netw; 1995; 6(5):1109-18. PubMed ID: 18263401
    [TBL] [Abstract][Full Text] [Related]  

  • 19. Toward a general-purpose analog VLSI neural network with on-chip learning.
    Montalvo AJ; Gyurcsik RS; Paulos JJ
    IEEE Trans Neural Netw; 1997; 8(2):413-23. PubMed ID: 18255643
    [TBL] [Abstract][Full Text] [Related]  

  • 20. Adaptive bidirectional associative memories.
    Kosko B
    Appl Opt; 1987 Dec; 26(23):4947-60. PubMed ID: 20523473
    [TBL] [Abstract][Full Text] [Related]  

    [Next]    [New Search]
    of 9.