These tools will no longer be maintained as of December 31, 2024. Archived website can be found here. PubMed4Hh GitHub repository can be found here. Contact NLM Customer Service if you have questions.
89 related articles for article (PubMed ID: 18276397)
1. A real-time experiment using a 50-neuron CMOS analog silicon chip with on-chip digital learning. Salam FA; Wang Y IEEE Trans Neural Netw; 1991; 2(4):461-4. PubMed ID: 18276397 [TBL] [Abstract][Full Text] [Related]
2. Neuron-synapse IC chip-set for large-scale chaotic neural networks. Horio Y; Aihara K; Yamamoto O IEEE Trans Neural Netw; 2003; 14(5):1393-404. PubMed ID: 18244585 [TBL] [Abstract][Full Text] [Related]
3. A programmable analog VLSI neural network processor for communication receivers. Choi J; Bang SH; Sheu BJ IEEE Trans Neural Netw; 1993; 4(3):484-95. PubMed ID: 18267752 [TBL] [Abstract][Full Text] [Related]
4. Chaotic neuron models and their VLSI circuit implementations. Hsu CC; Gobovic D; Zaghloul ME; Szu HH IEEE Trans Neural Netw; 1996; 7(6):1339-50. PubMed ID: 18263529 [TBL] [Abstract][Full Text] [Related]
5. An analog silicon retina with multichip configuration. Kameda S; Yagi T IEEE Trans Neural Netw; 2006 Jan; 17(1):197-210. PubMed ID: 16526487 [TBL] [Abstract][Full Text] [Related]
6. Specification and implementation of a digital Hopfield-type associative memory with on-chip training. Johannet A; Personnaz L; Dreyfus G; Gascuel JD; Weinfeld M IEEE Trans Neural Netw; 1992; 3(4):529-39. PubMed ID: 18276455 [TBL] [Abstract][Full Text] [Related]
7. An analog CMOS chip set for neural networks with arbitrary topologies. Lansner JA; Lehmann T IEEE Trans Neural Netw; 1993; 4(3):441-4. PubMed ID: 18267747 [TBL] [Abstract][Full Text] [Related]
8. Adaptive WTA with an analog VLSI neuromorphic learning chip. Häfliger P IEEE Trans Neural Netw; 2007 Mar; 18(2):551-72. PubMed ID: 17385639 [TBL] [Abstract][Full Text] [Related]
9. A VLSI neural processor for image data compression using self-organization networks. Fang WC; Sheu BJ; Chen OC; Choi J IEEE Trans Neural Netw; 1992; 3(3):506-18. PubMed ID: 18276454 [TBL] [Abstract][Full Text] [Related]
10. A CMOS analog adaptive BAM with on-chip learning and weight refreshing. Linares-Barranco B; Sanchez-Sinencio E; Rodriguez-Vazquez A; Huertas JL IEEE Trans Neural Netw; 1993; 4(3):445-55. PubMed ID: 18267748 [TBL] [Abstract][Full Text] [Related]
11. CMOS current-mode neural associative memory design with on-chip learning. Wu CY; Lan JF IEEE Trans Neural Netw; 1996; 7(1):167-81. PubMed ID: 18255567 [TBL] [Abstract][Full Text] [Related]
12. A CMOS binary pattern classifier based on Parzen's method. Coultrip R IEEE Trans Neural Netw; 1998; 9(1):2-10. PubMed ID: 18252424 [TBL] [Abstract][Full Text] [Related]
13. CMOS Ultrasound Transceiver Chip for High-Resolution Ultrasonic Imaging Systems. Insoo Kim ; Hyunsoo Kim ; Griggio F; Tutwiler RL; Jackson TN; Trolier-McKinstry S; Kyusun Choi IEEE Trans Biomed Circuits Syst; 2009 Oct; 3(5):293-303. PubMed ID: 23853268 [TBL] [Abstract][Full Text] [Related]
14. Toward a general-purpose analog VLSI neural network with on-chip learning. Montalvo AJ; Gyurcsik RS; Paulos JJ IEEE Trans Neural Netw; 1997; 8(2):413-23. PubMed ID: 18255643 [TBL] [Abstract][Full Text] [Related]
15. Analog VLSI Biophysical Neurons and Synapses With Programmable Membrane Channel Kinetics. Yu T; Cauwenberghs G IEEE Trans Biomed Circuits Syst; 2010 Jun; 4(3):139-48. PubMed ID: 23853338 [TBL] [Abstract][Full Text] [Related]
16. Frequency-based multilayer neural network with on-chip learning and enhanced neuron characteristics. Hikawa H IEEE Trans Neural Netw; 1999; 10(3):545-53. PubMed ID: 18252552 [TBL] [Abstract][Full Text] [Related]
17. An analog-digital hybrid RX beamformer chip with non-uniform sampling for ultrasound medical imaging with 2D CMUT array. Um JY; Kim YJ; Cho SE; Chae MK; Song J; Kim B; Lee S; Bang J; Kim Y; Cho K; Kim B; Sim JY; Park HJ IEEE Trans Biomed Circuits Syst; 2014 Dec; 8(6):799-809. PubMed ID: 25532209 [TBL] [Abstract][Full Text] [Related]
18. An ART1 microchip and its use in multi-ART1 systems. Serrano-Gotarrdeona T; Linares-Barranco B IEEE Trans Neural Netw; 1997; 8(5):1184-94. PubMed ID: 18255720 [TBL] [Abstract][Full Text] [Related]
19. Analysis and verification of an analog VLSI incremental outer-product learning system. Cauwenberghs G; Neugebauer CF; Yariv A IEEE Trans Neural Netw; 1992; 3(3):488-97. PubMed ID: 18276452 [TBL] [Abstract][Full Text] [Related]