These tools will no longer be maintained as of December 31, 2024. Archived website can be found here. PubMed4Hh GitHub repository can be found here. Contact NLM Customer Service if you have questions.
155 related articles for article (PubMed ID: 22049367)
1. Parallel programmable asynchronous neighborhood mechanism for Kohonen SOM implemented in CMOS technology. Długosz R; Kolasa M; Pedrycz W; Szulc M IEEE Trans Neural Netw; 2011 Dec; 22(12):2091-104. PubMed ID: 22049367 [TBL] [Abstract][Full Text] [Related]
2. A programmable triangular neighborhood function for a Kohonen self-organizing map implemented on chip. Kolasa M; Długosz R; Pedrycz W; Szulc M Neural Netw; 2012 Jan; 25(1):146-60. PubMed ID: 21964449 [TBL] [Abstract][Full Text] [Related]
3. Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology. Talaśka T; Kolasa M; Długosz R; Pedrycz W IEEE Trans Neural Netw Learn Syst; 2016 Mar; 27(3):661-73. PubMed ID: 26087501 [TBL] [Abstract][Full Text] [Related]
4. New adaptive color quantization method based on self-organizing maps. Chang CH; Xu P; Xiao R; Srikanthan T IEEE Trans Neural Netw; 2005 Jan; 16(1):237-49. PubMed ID: 15732403 [TBL] [Abstract][Full Text] [Related]
5. Neural CMOS-integrated circuit and its application to data classification. Göknar IC; Yildiz M; Minaei S; Deniz E IEEE Trans Neural Netw Learn Syst; 2012 May; 23(5):717-24. PubMed ID: 24806121 [TBL] [Abstract][Full Text] [Related]
6. Improved Learning Performance of Hardware Self-Organizing Map Using a Novel Neighborhood Function. Hikawa H; Maeda Y IEEE Trans Neural Netw Learn Syst; 2015 Nov; 26(11):2861-73. PubMed ID: 26484943 [TBL] [Abstract][Full Text] [Related]
7. Memristor bridge synapse-based neural network and its learning. Adhikari SP; Yang C; Kim H; Chua LO IEEE Trans Neural Netw Learn Syst; 2012 Sep; 23(9):1426-35. PubMed ID: 24807926 [TBL] [Abstract][Full Text] [Related]
8. Realization of the conscience mechanism in CMOS implementation of winner-takes-all self-organizing neural networks. Dlugosz R; Talaska T; Pedrycz W; Wojtyna R IEEE Trans Neural Netw; 2010 Jun; 21(6):961-71. PubMed ID: 20421180 [TBL] [Abstract][Full Text] [Related]
9. Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler. Minkovich K; Srinivasa N; Cruz-Albrecht JM; Cho Y; Nogin A IEEE Trans Neural Netw Learn Syst; 2012 Jun; 23(6):889-901. PubMed ID: 24806761 [TBL] [Abstract][Full Text] [Related]
10. An interval type-2 neural fuzzy chip with on-chip incremental learning ability for time-varying data sequence prediction and system control. Juang CF; Chen CY IEEE Trans Neural Netw Learn Syst; 2014 Jan; 25(1):216-28. PubMed ID: 24806655 [TBL] [Abstract][Full Text] [Related]
11. Simultaneous perturbation learning rule for recurrent neural networks and its FPGA implementation. Maeda Y; Wakamura M IEEE Trans Neural Netw; 2005 Nov; 16(6):1664-72. PubMed ID: 16342505 [TBL] [Abstract][Full Text] [Related]
12. A 128-channel 6 mW wireless neural recording IC with spike feature extraction and UWB transmitter. Chae MS; Yang Z; Yuce MR; Hoang L; Liu W IEEE Trans Neural Syst Rehabil Eng; 2009 Aug; 17(4):312-21. PubMed ID: 19435684 [TBL] [Abstract][Full Text] [Related]
13. Machine learning on-a-chip: a high-performance low-power reusable neuron architecture for artificial neural networks in ECG classifications. Sun Y; Cheng AC Comput Biol Med; 2012 Jul; 42(7):751-7. PubMed ID: 22595230 [TBL] [Abstract][Full Text] [Related]
14. Analog CMOS circuit design and characterization for optical coherence tomography signal processing. Kariya R; Mathine DL; Barton JK IEEE Trans Biomed Eng; 2004 Dec; 51(12):2160-3. PubMed ID: 15605863 [TBL] [Abstract][Full Text] [Related]
15. Analog implementation of a Kohonen map with on-chip learning. Macq D; Verleysen M; Jespers P; Legat JD IEEE Trans Neural Netw; 1993; 4(3):456-61. PubMed ID: 18267749 [TBL] [Abstract][Full Text] [Related]
16. A CMOS image sensor with programmable pixel-level analog processing. Massari N; Gottardi M; Gonzo L; Stoppa D; Simoni A IEEE Trans Neural Netw; 2005 Nov; 16(6):1673-84. PubMed ID: 16342506 [TBL] [Abstract][Full Text] [Related]
17. An ultra low-power CMOS automatic action potential detector. Gosselin B; Sawan M IEEE Trans Neural Syst Rehabil Eng; 2009 Aug; 17(4):346-53. PubMed ID: 19366647 [TBL] [Abstract][Full Text] [Related]
18. O(log2 M) self-organizing map algorithm without learning of neighborhood vectors. Kusumoto H; Takefuji Y IEEE Trans Neural Netw; 2006 Nov; 17(6):1656-61. PubMed ID: 17131681 [TBL] [Abstract][Full Text] [Related]
19. Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process. Rahman LF; Reaz MB; Yin CC; Ali MA; Marufuzzaman M PLoS One; 2014; 9(10):e108634. PubMed ID: 25299266 [TBL] [Abstract][Full Text] [Related]
20. A low-voltage wide-input CMOS comparator for sensor application using back-gate technique. Hung YC; Liu BD Biosens Bioelectron; 2004 Jul; 20(1):53-9. PubMed ID: 15142576 [TBL] [Abstract][Full Text] [Related] [Next] [New Search]