151 related articles for article (PubMed ID: 26055484)
1. Novel 14-nm Scallop-Shaped FinFETs (S-FinFETs) on Bulk-Si Substrate.
Xu W; Yin H; Ma X; Hong P; Xu M; Meng L
Nanoscale Res Lett; 2015 Dec; 10(1):958. PubMed ID: 26055484
[TBL] [Abstract][Full Text] [Related]
2. Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO
Yan SC; Wu CH; Sun CJ; Lin YW; Yao YJ; Wu YC
Nanomaterials (Basel); 2022 Jun; 12(13):. PubMed ID: 35807999
[TBL] [Abstract][Full Text] [Related]
3. Development and Analysis of a Three-Fin Trigate Q-FinFET for a 3 nm Technology Node with a Strained-Silicon Channel System.
Nanda S; Dhar RS; Awwad F; Hussein MI
Nanomaterials (Basel); 2023 May; 13(10):. PubMed ID: 37242078
[TBL] [Abstract][Full Text] [Related]
4. Sensing with Advanced Computing Technology: Fin Field-Effect Transistors with High-k Gate Stack on Bulk Silicon.
Rigante S; Scarbolo P; Wipf M; Stoop RL; Bedner K; Buitrago E; Bazigos A; Bouvet D; Calame M; Schönenberger C; Ionescu AM
ACS Nano; 2015 May; 9(5):4872-81. PubMed ID: 25817336
[TBL] [Abstract][Full Text] [Related]
5. Electrical characteristic fluctuation of 16-nm-gate high-κ/metal gate bulk FinFET devices in the presence of random interface traps.
Hsu SC; Li Y
Nanoscale Res Lett; 2014; 9(1):633. PubMed ID: 25520590
[TBL] [Abstract][Full Text] [Related]
6. Can ultra-thin Si FinFETs work well in the sub-10 nm gate-length region?
Liu S; Yang J; Xu L; Li J; Yang C; Li Y; Shi B; Pan Y; Xu L; Ma J; Yang J; Lu J
Nanoscale; 2021 Mar; 13(10):5536-5544. PubMed ID: 33688887
[TBL] [Abstract][Full Text] [Related]
7. Electrical characteristic fluctuation of 16-nm-gate trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants.
Huang WT; Li Y
Nanoscale Res Lett; 2015; 10():116. PubMed ID: 25897299
[TBL] [Abstract][Full Text] [Related]
8. InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities.
Convertino C; Zota C; Schmid H; Caimi D; Sousa M; Moselund K; Czornomaz L
Materials (Basel); 2018 Dec; 12(1):. PubMed ID: 30591676
[TBL] [Abstract][Full Text] [Related]
9. Effects of Random Nanosized TiN Grain on Characteristic of Gate-All-Around FinFETs with Ferroelectric HZO Layer.
Li Y; Chuang MH; Tsai YC
Nanoscale Res Lett; 2022 Jan; 17(1):16. PubMed ID: 35061127
[TBL] [Abstract][Full Text] [Related]
10. A Feasible Alternative to FDSOI and FinFET: Optimization of W/La
Mah SK; Ker PJ; Ahmad I; Zainul Abidin NF; Ali Gamel MM
Materials (Basel); 2021 Sep; 14(19):. PubMed ID: 34640118
[TBL] [Abstract][Full Text] [Related]
11. Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices.
Zhang Q; Gu J; Xu R; Cao L; Li J; Wu Z; Wang G; Yao J; Zhang Z; Xiang J; He X; Kong Z; Yang H; Tian J; Xu G; Mao S; Radamson HH; Yin H; Luo J
Nanomaterials (Basel); 2021 Mar; 11(3):. PubMed ID: 33808024
[TBL] [Abstract][Full Text] [Related]
12. Nonplanar Nanoscale Fin Field Effect Transistors on Textile, Paper, Wood, Stone, and Vinyl via Soft Material-Enabled Double-Transfer Printing.
Rojas JP; Torres Sevilla GA; Alfaraj N; Ghoneim MT; Kutbee AT; Sridharan A; Hussain MM
ACS Nano; 2015 May; 9(5):5255-63. PubMed ID: 25933370
[TBL] [Abstract][Full Text] [Related]
13. Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study.
Ülkü A; Uçar E; Serin RB; Kaçar R; Artuç M; Menşur E; Oral AY
Micromachines (Basel); 2024 May; 15(6):. PubMed ID: 38930696
[TBL] [Abstract][Full Text] [Related]
14. Experimental study on the subthreshold swing of silicon nanowire transistors.
Zhang Y; Xiong Y; Yang X; Wang Y; Han W; Yang F
J Nanosci Nanotechnol; 2010 Nov; 10(11):7113-6. PubMed ID: 21137876
[TBL] [Abstract][Full Text] [Related]
15. High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET.
Yao YJ; Yang CR; Tseng TY; Chang HJ; Lin TJ; Luo GL; Hou FJ; Wu YC; Chang-Liao KS
Nanomaterials (Basel); 2023 Apr; 13(8):. PubMed ID: 37110895
[TBL] [Abstract][Full Text] [Related]
16. Asymmetric Drain Extension Dual-kk Trigate Underlap FinFET Based on RF/Analog Circuit.
Han K; Qiao G; Deng Z; Zhang Y
Micromachines (Basel); 2017 Nov; 8(11):. PubMed ID: 30400520
[TBL] [Abstract][Full Text] [Related]
17. Low-temperature performance of accumulation-mode p-channel wrap-gated FinFETs.
Zhang Y; Du Y; Chen Y; Lil X; Yang X; Han W; Yang F
J Nanosci Nanotechnol; 2013 Feb; 13(2):804-7. PubMed ID: 23646519
[TBL] [Abstract][Full Text] [Related]
18. Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around.
Guerfi Y; Larrieu G
Nanoscale Res Lett; 2016 Dec; 11(1):210. PubMed ID: 27094824
[TBL] [Abstract][Full Text] [Related]
19. The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length.
Saha P; Sankar Dhar R; Nanda S; Kumar K; Alathbah M
Nanomaterials (Basel); 2023 Nov; 13(23):. PubMed ID: 38063707
[TBL] [Abstract][Full Text] [Related]
20. Three-Dimensional Nanoscale Mapping of State-of-the-Art Field-Effect Transistors (FinFETs).
Parikh P; Senowitz C; Lyons D; Martin I; Prosa TJ; DiBattista M; Devaraj A; Meng YS
Microsc Microanal; 2017 Oct; 23(5):916-925. PubMed ID: 28854989
[TBL] [Abstract][Full Text] [Related]
[Next] [New Search]
