490 related articles for article (PubMed ID: 29993989)
21. Performance analysis of multiple input single layer neural network hardware chip.
Goel A; Goel AK; Kumar A
Multimed Tools Appl; 2023 Feb; ():1-22. PubMed ID: 36846531
[TBL] [Abstract][Full Text] [Related]
22. Low-Power Hardware Implementation of a Support Vector Machine Training and Classification for Neural Seizure Detection.
Elhosary H; Zakhari MH; Elgammal MA; Abd El Ghany MA; Salama KN; Mostafa H
IEEE Trans Biomed Circuits Syst; 2019 Dec; 13(6):1324-1337. PubMed ID: 31613779
[TBL] [Abstract][Full Text] [Related]
23. X-Ray Tomography Reconstruction Accelerated on FPGA Through High-Level Synthesis Tools.
Diakite D; Gac N
IEEE Trans Biomed Circuits Syst; 2023 Apr; 17(2):375-389. PubMed ID: 37030851
[TBL] [Abstract][Full Text] [Related]
24. A Low Memory Requirement MobileNets Accelerator Based on FPGA for Auxiliary Medical Tasks.
Lin Y; Zhang Y; Yang X
Bioengineering (Basel); 2022 Dec; 10(1):. PubMed ID: 36671600
[TBL] [Abstract][Full Text] [Related]
25. [Thalamocortical Neural Mass Model Simulation and Study Based on Field Programmable Gate Array].
Liang Z; Zhou J; Li X
Sheng Wu Yi Xue Gong Cheng Xue Za Zhi; 2016 Aug; 33(4):616-25. PubMed ID: 29714455
[TBL] [Abstract][Full Text] [Related]
26. Optimizing the Deep Neural Networks by Layer-Wise Refined Pruning and the Acceleration on FPGA.
Li H; Yue X; Wang Z; Chai Z; Wang W; Tomiyama H; Meng L
Comput Intell Neurosci; 2022; 2022():8039281. PubMed ID: 35694575
[TBL] [Abstract][Full Text] [Related]
27. SOMprocessor: A high throughput FPGA-based architecture for implementing Self-Organizing Maps and its application to video processing.
Sousa MAA; Pires R; Del-Moral-Hernandez E
Neural Netw; 2020 May; 125():349-362. PubMed ID: 32179330
[TBL] [Abstract][Full Text] [Related]
28. FPNA: interaction between FPGA and neural computation.
Girau B
Int J Neural Syst; 2000 Jun; 10(3):243-59. PubMed ID: 11011795
[TBL] [Abstract][Full Text] [Related]
29. FPGA Implementation of the Coupled Filtering Method and the Affine Warping Method.
Zhang C; Liang T; Mok PKT; Yu W
IEEE Trans Nanobioscience; 2017 Jul; 16(5):314-325. PubMed ID: 28534779
[TBL] [Abstract][Full Text] [Related]
30. A Novel Memory-Scheduling Strategy for Large Convolutional Neural Network on Memory-Limited Devices.
Li S; Shen X; Dou Y; Ni S; Xu J; Yang K; Wang Q; Niu X
Comput Intell Neurosci; 2019; 2019():4328653. PubMed ID: 31182958
[TBL] [Abstract][Full Text] [Related]
31. Research on OpenCL optimization for FPGA deep learning application.
Zhang S; Wu Y; Men C; He H; Liang K
PLoS One; 2019; 14(10):e0222984. PubMed ID: 31600218
[TBL] [Abstract][Full Text] [Related]
32. A forecast-based STDP rule suitable for neuromorphic implementation.
Davies S; Galluppi F; Rast AD; Furber SB
Neural Netw; 2012 Aug; 32():3-14. PubMed ID: 22386500
[TBL] [Abstract][Full Text] [Related]
33. Mass detection in digital breast tomosynthesis: Deep convolutional neural network with transfer learning from mammography.
Samala RK; Chan HP; Hadjiiski L; Helvie MA; Wei J; Cha K
Med Phys; 2016 Dec; 43(12):6654. PubMed ID: 27908154
[TBL] [Abstract][Full Text] [Related]
34. FTA-GAN: A Computation-Efficient Accelerator for GANs With Fast Transformation Algorithm.
Mao W; Yang P; Wang Z
IEEE Trans Neural Netw Learn Syst; 2023 Jun; 34(6):2978-2992. PubMed ID: 34534090
[TBL] [Abstract][Full Text] [Related]
35. Compression of Deep Neural Networks based on quantized tensor decomposition to implement on reconfigurable hardware platforms.
Nekooei A; Safari S
Neural Netw; 2022 Jun; 150():350-363. PubMed ID: 35344706
[TBL] [Abstract][Full Text] [Related]
36. A 128-Channel FPGA-Based Real-Time Spike-Sorting Bidirectional Closed-Loop Neural Interface System.
Park J; Kim G; Jung SD
IEEE Trans Neural Syst Rehabil Eng; 2017 Dec; 25(12):2227-2238. PubMed ID: 28459692
[TBL] [Abstract][Full Text] [Related]
37. An FPGA Implementation of Deep Spiking Neural Networks for Low-Power and Fast Classification.
Ju X; Fang B; Yan R; Xu X; Tang H
Neural Comput; 2020 Jan; 32(1):182-204. PubMed ID: 31703174
[TBL] [Abstract][Full Text] [Related]
38. FPGA Implementation for Odor Identification with Depthwise Separable Convolutional Neural Network.
Mo Z; Luo D; Wen T; Cheng Y; Li X
Sensors (Basel); 2021 Jan; 21(3):. PubMed ID: 33513692
[TBL] [Abstract][Full Text] [Related]
39. Machine learning on-a-chip: a high-performance low-power reusable neuron architecture for artificial neural networks in ECG classifications.
Sun Y; Cheng AC
Comput Biol Med; 2012 Jul; 42(7):751-7. PubMed ID: 22595230
[TBL] [Abstract][Full Text] [Related]
40. [Hardware Implementation of Numerical Simulation Function of Hodgkin-Huxley Model Neurons Action Potential Based on Field Programmable Gate Array].
Wang J; Lu M; Hu Y; Chen X; Pan Q
Sheng Wu Yi Xue Gong Cheng Xue Za Zhi; 2015 Dec; 32(6):1302-9. PubMed ID: 27079105
[TBL] [Abstract][Full Text] [Related]
[Previous] [Next] [New Search]