These tools will no longer be maintained as of December 31, 2024. Archived website can be found here. PubMed4Hh GitHub repository can be found here. Contact NLM Customer Service if you have questions.
312 related articles for article (PubMed ID: 31683726)
1. Design and Optimization of Germanium-Based Gate-Metal-Core Vertical Nanowire Tunnel FET. Jang WD; Yoon YJ; Cho MS; Jung JH; Lee SH; Jang J; Bae JH; Kang IM Micromachines (Basel); 2019 Oct; 10(11):. PubMed ID: 31683726 [TBL] [Abstract][Full Text] [Related]
2. A Novel Germanium-Around-Source Gate-All-Around tunnelling Field-Effect Transistor for Low-Power Applications. Han K; Long S; Deng Z; Zhang Y; Li J Micromachines (Basel); 2020 Feb; 11(2):. PubMed ID: 32028719 [TBL] [Abstract][Full Text] [Related]
3. Design Optimization of Ge/GaAs-Based Heterojunction Gate-All-Around (GAA) Arch-Shaped Tunneling Field-Effect Transistor (A-TFET). Seo JH; Yoon YJ; Kang IM J Nanosci Nanotechnol; 2018 Sep; 18(9):6602-6605. PubMed ID: 29677842 [TBL] [Abstract][Full Text] [Related]
4. Design Optimization of InGaAs/GaAsSb-Based Kim BG; Seo JH; Yoon YJ; Cho MS; Kang IM J Nanosci Nanotechnol; 2019 Oct; 19(10):6762-6766. PubMed ID: 31027025 [TBL] [Abstract][Full Text] [Related]
5. Vertical Tunnel Field-Effect Transistor with Polysilicon Layer. Lee WJ; Kwon HT; Choi HS; Wee D; Park YJ; Kim B; Kim Y J Nanosci Nanotechnol; 2019 Oct; 19(10):6722-6726. PubMed ID: 31027017 [TBL] [Abstract][Full Text] [Related]
6. Surrounding Channel Nanowire Tunnel Field-Effect Transistor with Dual Gate to Reduce a Hump Phenomenon. Kwon YS; Lee SH; Kim Y; Kim G; Kim JH; Kim S J Nanosci Nanotechnol; 2020 Jul; 20(7):4182-4187. PubMed ID: 31968438 [TBL] [Abstract][Full Text] [Related]
7. Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor. Chen S; Liu H; Wang S; Li W; Wang X; Zhao L Nanoscale Res Lett; 2018 Oct; 13(1):321. PubMed ID: 30315380 [TBL] [Abstract][Full Text] [Related]
8. Switching performance assessment of gate-all-around InAs-Si vertical TFET with triple metal gate, a simulation study. Madadi D; Mohammadi S Discov Nano; 2023 Mar; 18(1):37. PubMed ID: 37382780 [TBL] [Abstract][Full Text] [Related]
9. Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs. Vasen T; Ramvall P; Afzalian A; Doornbos G; Holland M; Thelander C; Dick KA; Wernersson L-; Passlack M Sci Rep; 2019 Jan; 9(1):202. PubMed ID: 30655575 [TBL] [Abstract][Full Text] [Related]
10. Design Optimization of Double-Gate Isosceles Trapezoid Tunnel Field-Effect Transistor (DGIT-TFET). Gu HY; Kim S Micromachines (Basel); 2019 Mar; 10(4):. PubMed ID: 30935007 [TBL] [Abstract][Full Text] [Related]
11. High performance tunnel field-effect transistor by gate and source engineering. Huang R; Huang Q; Chen S; Wu C; Wang J; An X; Wang Y Nanotechnology; 2014 Dec; 25(50):505201. PubMed ID: 25427134 [TBL] [Abstract][Full Text] [Related]
12. Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate. Li W; Liu H; Wang S; Chen S; Yang Z Nanoscale Res Lett; 2017 Dec; 12(1):198. PubMed ID: 28314362 [TBL] [Abstract][Full Text] [Related]
13. Analysis of Channel Area Fluctuation Effects of Gate-All-Around Tunnel Field-Effect Transistor. Kang SJ; Park JU; Rim KJ; Kim Y; Kim JH; Kim G; Kim S J Nanosci Nanotechnol; 2020 Jul; 20(7):4409-4413. PubMed ID: 31968485 [TBL] [Abstract][Full Text] [Related]
14. FS-iTFET: advancing tunnel FET technology with Schottky-inductive source and GAA design. Lin JT; Tai WH Discov Nano; 2024 Sep; 19(1):140. PubMed ID: 39227488 [TBL] [Abstract][Full Text] [Related]
15. Design and Analysis of CMOS-Compatible III-V Compound Electron-Hole Bilayer Tunneling Field-Effect Transistor for Ultra-Low-Power Applications. Kim SY; Seo JH; Yoon YJ; Lee HY; Lee SM; Cho S; Kang IM J Nanosci Nanotechnol; 2015 Oct; 15(10):7486-92. PubMed ID: 26726356 [TBL] [Abstract][Full Text] [Related]
16. Design and analysis of vertical-channel gallium nitride (GaN) junctionless nanowire transistors (JNT). Seo JH; Yoon YJ; Lee HG; Yoo GM; Jo YW; Son DH; Lee JH; Cho ES; Cho S; Kang IM J Nanosci Nanotechnol; 2014 Nov; 14(11):8130-5. PubMed ID: 25958486 [TBL] [Abstract][Full Text] [Related]
17. Analysis of Current Variation with Work Function Variation in L-Shaped Tunnel-Field Effect Transistor. Kim JH; Kim HW; Song YS; Kim S; Kim G Micromachines (Basel); 2020 Aug; 11(8):. PubMed ID: 32824238 [TBL] [Abstract][Full Text] [Related]
18. I-Shaped SiGe Fin Tunnel Field-Effect Transistor with High Lee R; Lee J; Lee K; Kim S; Kim S; Kim S; Park BG J Nanosci Nanotechnol; 2020 Jul; 20(7):4298-4302. PubMed ID: 31968461 [TBL] [Abstract][Full Text] [Related]
19. Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET. Yang Z; Yang Y; Yu N; Liou JJ Micromachines (Basel); 2018 Dec; 9(12):. PubMed ID: 30545073 [TBL] [Abstract][Full Text] [Related]
20. Study of a Gate-Engineered Vertical TFET with GaSb/GaAs Xie H; Chen Y; Liu H; Guo D Materials (Basel); 2021 Mar; 14(6):. PubMed ID: 33804142 [TBL] [Abstract][Full Text] [Related] [Next] [New Search]