108 related articles for article (PubMed ID: 32604484)
1. Analysis of Logic Inverter Based on Polycrystalline Silicon with Single Grain Boundary.
Mun HJ; Cho MS; Jung JH; Jang WD; Lee SH; Jang J; Bae JH; Kang IM
J Nanosci Nanotechnol; 2020 Nov; 20(11):6616-6621. PubMed ID: 32604484
[TBL] [Abstract][Full Text] [Related]
2. Analysis of CMOS Logic Inverter Based on Gate-All-Around Field-Effect Transistors with the Strained-Silicon Layer for Improving the Switching Performances.
Lee SH; Cho MS; Jung JH; Jang WD; Mun HJ; Jang J; Bae JH; Kang IM
J Nanosci Nanotechnol; 2020 Nov; 20(11):6632-6637. PubMed ID: 32604487
[TBL] [Abstract][Full Text] [Related]
3. Temperature Dependence According to Grain Boundary Potential Barrier Variation in Vertical NAND Flash Cell with Polycrystalline-Silicon Channel.
Yang HJ; Oh YT; Kim KB; Kweon JY; Lee GH; Choi ES; Park SK; Song YH
J Nanosci Nanotechnol; 2017 Apr; 17(4):2628-632. PubMed ID: 29664250
[TBL] [Abstract][Full Text] [Related]
4. High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.
Van NH; Lee JH; Sohn JI; Cha SN; Whang D; Kim JM; Kang DJ
Nanoscale; 2014 May; 6(10):5479-83. PubMed ID: 24727896
[TBL] [Abstract][Full Text] [Related]
5. Simulation of Total Ionizing Dose Effects Technique for CMOS Inverter Circuit.
Gao T; Yin C; Chen Y; Chen R; Yan C; Liu H
Micromachines (Basel); 2023 Jul; 14(7):. PubMed ID: 37512749
[TBL] [Abstract][Full Text] [Related]
6. Effects of the Grain Boundary and Interface Traps on the Electrical Characteristics of 3D NAND Flash Memory Devices.
Lee JG; Kim TW
J Nanosci Nanotechnol; 2018 Mar; 18(3):1944-1947. PubMed ID: 29448689
[TBL] [Abstract][Full Text] [Related]
7. Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks.
Zhao Y; Li Q; Xiao X; Li G; Jin Y; Jiang K; Wang J; Fan S
ACS Nano; 2016 Feb; 10(2):2193-202. PubMed ID: 26768020
[TBL] [Abstract][Full Text] [Related]
8. Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.
Das T; Chen X; Jang H; Oh IK; Kim H; Ahn JH
Small; 2016 Nov; 12(41):5720-5727. PubMed ID: 27608439
[TBL] [Abstract][Full Text] [Related]
9. Design and Simulation of Logic-In-Memory Inverter Based on a Silicon Nanowire Feedback Field-Effect Transistor.
Baek E; Son J; Cho K; Kim S
Micromachines (Basel); 2022 Apr; 13(4):. PubMed ID: 35457895
[TBL] [Abstract][Full Text] [Related]
10. Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors.
Van NH; Lee JH; Whang D; Kang DJ
Nanoscale; 2016 Jun; 8(23):12022-8. PubMed ID: 27240692
[TBL] [Abstract][Full Text] [Related]
11. Dependence of Grain Size on the Performance of a Polysilicon Channel TFT for 3D NAND Flash Memory.
Kim SY; Park JK; Hwang WS; Lee SJ; Lee KH; Pyi SH; Cho BJ
J Nanosci Nanotechnol; 2016 May; 16(5):5044-8. PubMed ID: 27483868
[TBL] [Abstract][Full Text] [Related]
12. New ternary inverter with memory function using silicon feedback field-effect transistors.
Son J; Cho K; Kim S
Sci Rep; 2022 Jul; 12(1):12907. PubMed ID: 35902615
[TBL] [Abstract][Full Text] [Related]
13. MoS
Liu F; Zhang Y; Wang J; Chen Y; Wang L; Wang G; Dong J; Jiang C
Nanotechnology; 2021 Jan; 32(1):015203. PubMed ID: 32947272
[TBL] [Abstract][Full Text] [Related]
14. Low-power-consumption CMOS inverter array based on CVD-grown
Du W; Jia X; Cheng Z; Xu W; Li Y; Dai L
iScience; 2021 Dec; 24(12):103491. PubMed ID: 34917894
[TBL] [Abstract][Full Text] [Related]
15. An Analysis of Hole Trapping at Grain Boundary or Poly-Si Floating-Body MOSFET.
Jang T; Baek MH; Kim H; Park BG
J Nanosci Nanotechnol; 2018 Sep; 18(9):6584-6587. PubMed ID: 29677838
[TBL] [Abstract][Full Text] [Related]
16. Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters.
Luo H; Liang L; Cao H; Dai M; Lu Y; Wang M
ACS Appl Mater Interfaces; 2015 Aug; 7(31):17023-31. PubMed ID: 26189702
[TBL] [Abstract][Full Text] [Related]
17. Nanowire NMOS Logic Inverter Characterization.
Hashim Y
J Nanosci Nanotechnol; 2016 Jun; 16(6):5923-8. PubMed ID: 27427653
[TBL] [Abstract][Full Text] [Related]
18. Mechanically Flexible and High-Performance CMOS Logic Circuits.
Honda W; Arie T; Akita S; Takei K
Sci Rep; 2015 Oct; 5():15099. PubMed ID: 26459882
[TBL] [Abstract][Full Text] [Related]
19. Fabrication of stretchable single-walled carbon nanotube logic devices.
Yoon J; Shin G; Kim J; Moon YS; Lee SJ; Zi G; Ha JS
Small; 2014 Jul; 10(14):2910-7. PubMed ID: 24700788
[TBL] [Abstract][Full Text] [Related]
20. Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries.
Park J; Lee SH; Kang GE; Heo JH; Jeon SR; Kim MS; Bae SJ; Hong JW; Jang JW; Bae JH; Lee SH; Kang IM
Nanomaterials (Basel); 2023 Jul; 13(13):. PubMed ID: 37446542
[TBL] [Abstract][Full Text] [Related]
[Next] [New Search]