These tools will no longer be maintained as of December 31, 2024. Archived website can be found here. PubMed4Hh GitHub repository can be found here. Contact NLM Customer Service if you have questions.
160 related articles for article (PubMed ID: 33714307)
1. Design of a Capacitorless Dynamic Random Access Memory Based on Ultra-Thin Polycrystalline Silicon Junctionless Field-Effect Transistor with Dual-Gate. Lee SH; Cho MS; Jung JH; Jang WD; Mun HJ; Jang J; Bae JH; Kang IM J Nanosci Nanotechnol; 2021 Aug; 21(8):4223-4229. PubMed ID: 33714307 [TBL] [Abstract][Full Text] [Related]
2. Design of a Capacitorless Dynamic Random Access Memory Based on Junctionless Dual-Gate Field-Effect Transistor with a Silicon-Germanium/Silicon Nanotube. Lee SH; Cho MS; Mun HJ; Park J; An HD; Jang J; Bae JH; Kang IM J Nanosci Nanotechnol; 2021 Aug; 21(8):4235-4242. PubMed ID: 33714309 [TBL] [Abstract][Full Text] [Related]
3. Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure. An HD; Lee SH; Park J; Min SR; Kim GU; Yoon YJ; Seo JH; Cho MS; Jang J; Bae JH; Lee SH; Kang IM Nanomaterials (Basel); 2022 Oct; 12(19):. PubMed ID: 36234653 [TBL] [Abstract][Full Text] [Related]
4. Simulation for Electrical Performances of the Capacitorless Dynamic Random Access Memory Based on Junctionless FinFETs. Cho MS; Yoon YJ; Kim BG; Jung JH; Jang WD; Lee JH; Kang IM J Nanosci Nanotechnol; 2019 Oct; 19(10):6755-6761. PubMed ID: 31027024 [TBL] [Abstract][Full Text] [Related]
5. Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries. Park J; Lee SH; Kang GE; Heo JH; Jeon SR; Kim MS; Bae SJ; Hong JW; Jang JW; Bae JH; Lee SH; Kang IM Nanomaterials (Basel); 2023 Jul; 13(13):. PubMed ID: 37446542 [TBL] [Abstract][Full Text] [Related]
6. Capacitorless One-Transistor Dynamic Random-Access Memory Based on Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with Si/SiGe Heterojunction and Underlap Structure for Improvement of Sensing Margin and Retention Time. Yoon YJ; Cho MS; Kim BG; Seo JH; Kang IM J Nanosci Nanotechnol; 2019 Oct; 19(10):6023-6030. PubMed ID: 31026902 [TBL] [Abstract][Full Text] [Related]
7. Capacitorless One-Transistor Dynamic Random-Access Memory with Novel Mechanism: Self-Refreshing. Lee SH; Park J; Yoon YJ; Kang IM Nanomaterials (Basel); 2024 Jan; 14(2):. PubMed ID: 38251143 [TBL] [Abstract][Full Text] [Related]
8. Simulation of One-Transistor Dynamic Random-Access Memory Based on Symmetric Double-Gate Si Junctionless Transistor. Kim BG; Seo JH; Yoon YJ; Cho MS; Yu E; Lee JH; Cho S; Kang IM J Nanosci Nanotechnol; 2018 Sep; 18(9):6593-6597. PubMed ID: 29677840 [TBL] [Abstract][Full Text] [Related]
9. The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET. Li W; Liu H; Wang S; Chen S; Wang Q Nanoscale Res Lett; 2017 Sep; 12(1):524. PubMed ID: 28875269 [TBL] [Abstract][Full Text] [Related]
10. Capacitorless 1T-DRAM on crystallized poly-Si TFT. Kim MS; Cho WJ J Nanosci Nanotechnol; 2011 Jul; 11(7):5608-11. PubMed ID: 22121578 [TBL] [Abstract][Full Text] [Related]
11. 3-D stacked polycrystalline-silicon-MOSFET-based capacitorless DRAM with superior immunity to grain-boundary's influence. Lee SH; Park J; Min SR; Kim GU; Jang J; Bae JH; Lee SH; Kang IM Sci Rep; 2022 Aug; 12(1):14455. PubMed ID: 36002621 [TBL] [Abstract][Full Text] [Related]
12. Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM. Yoo S; Sun W; Shin H Micromachines (Basel); 2020 Oct; 11(11):. PubMed ID: 33105643 [TBL] [Abstract][Full Text] [Related]
13. Design and Analysis of Metal-Oxide-Semiconductor Field-Effect Transistor-Based Capacitorless One-Transistor Embedded Dynamic Random-Access Memory with Double-Polysilicon Layer Using Grain Boundary for Hole Storage. Jang WD; Yoon YJ; Cho MS; Jung JH; Lee SH; Jang J; Bae JH; Kang IM J Nanosci Nanotechnol; 2020 Nov; 20(11):6596-6602. PubMed ID: 32604481 [TBL] [Abstract][Full Text] [Related]
14. A Novel Capacitorless 1T DRAM with Embedded Oxide Layer. Zhao D; Xia Z; Yang T; Yang Y; Zhou W; Huo Z Micromachines (Basel); 2022 Oct; 13(10):. PubMed ID: 36296125 [TBL] [Abstract][Full Text] [Related]
15. The Effect of Grain Boundary on Electrical Characteristics in the Source and Drain Regions of Polycrystalline Silicon Based in One Transistor Dynamic Random Access Memory. An HD; Cho MS; Mun HJ; Lee SH; Park J; Jang J; Bae JH; Kang IM J Nanosci Nanotechnol; 2021 Aug; 21(8):4258-4267. PubMed ID: 33714312 [TBL] [Abstract][Full Text] [Related]
16. Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM. Kim H; Yoo S; Kang IM; Cho S; Sun W; Shin H Micromachines (Basel); 2020 Feb; 11(2):. PubMed ID: 32102235 [TBL] [Abstract][Full Text] [Related]
17. Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM. Ha Y; Shin H; Sun W; Park J Micromachines (Basel); 2021 Oct; 12(10):. PubMed ID: 34683260 [TBL] [Abstract][Full Text] [Related]
18. Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure. Kim HM; Kwon DW; Kim S; Lee K; Lee J; Park E; Lee R; Kim H; Kim S; Park BG J Nanosci Nanotechnol; 2018 Sep; 18(9):5882-5886. PubMed ID: 29677710 [TBL] [Abstract][Full Text] [Related]
19. Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory. Yoo S; Kang IM; Cho SJ; Sun W; Shin H J Nanosci Nanotechnol; 2021 Aug; 21(8):4216-4222. PubMed ID: 33714306 [TBL] [Abstract][Full Text] [Related]
20. Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors. Jeon J; Cho K; Kim S Micromachines (Basel); 2023 May; 14(6):. PubMed ID: 37374723 [TBL] [Abstract][Full Text] [Related] [Next] [New Search]