These tools will no longer be maintained as of December 31, 2024. Archived website can be found here. PubMed4Hh GitHub repository can be found here. Contact NLM Customer Service if you have questions.


BIOMARKERS

Molecular Biopsy of Human Tumors

- a resource for Precision Medicine *

114 related articles for article (PubMed ID: 34564101)

  • 1.
    Tekleyohannes MK; Rybalkin V; Ghaffar MM; Varela JA; Wehn N; Dengel A
    J Imaging; 2021 Sep; 7(9):. PubMed ID: 34564101
    [TBL] [Abstract][Full Text] [Related]  

  • 2. A fully-mapped and energy-efficient FPGA accelerator for dual-function AI-based analysis of ECG.
    Liu W; Guo Q; Chen S; Chang S; Wang H; He J; Huang Q
    Front Physiol; 2023; 14():1079503. PubMed ID: 36814476
    [TBL] [Abstract][Full Text] [Related]  

  • 3. Accelerating GRAPPA reconstruction using SoC design for real-time cardiac MRI.
    Basit A; Inam O; Omer H
    Comput Biol Med; 2023 Jun; 160():107008. PubMed ID: 37159960
    [TBL] [Abstract][Full Text] [Related]  

  • 4. Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network.
    Shah N; Chaudhari P; Varghese K
    IEEE Trans Neural Netw Learn Syst; 2018 Dec; 29(12):5922-5934. PubMed ID: 29993989
    [TBL] [Abstract][Full Text] [Related]  

  • 5. FPGA-Based Processor Acceleration for Image Processing Applications.
    Siddiqui F; Amiri S; Minhas UI; Deng T; Woods R; Rafferty K; Crookes D
    J Imaging; 2019 Jan; 5(1):. PubMed ID: 34465705
    [TBL] [Abstract][Full Text] [Related]  

  • 6. Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip.
    Perri S; Sestito C; Spagnolo F; Corsonello P
    J Imaging; 2020 Aug; 6(9):. PubMed ID: 34460742
    [TBL] [Abstract][Full Text] [Related]  

  • 7. FPGA-based hardware accelerator for SENSE (a parallel MR image reconstruction method).
    Inam O; Basit A; Qureshi M; Omer H
    Comput Biol Med; 2020 Feb; 117():103598. PubMed ID: 32072979
    [TBL] [Abstract][Full Text] [Related]  

  • 8. An Image Histogram Equalization Acceleration Method for Field-Programmable Gate Arrays Based on a Two-Dimensional Configurable Pipeline.
    Wang Y; Liu P; Li D; Wang K; Zhang R
    Sensors (Basel); 2024 Jan; 24(1):. PubMed ID: 38203143
    [TBL] [Abstract][Full Text] [Related]  

  • 9. Runtime and Architecture Support for Efficient Data Exchange in Multi-Accelerator Applications.
    Cabezas J; Gelado I; Stone JE; Navarro N; Kirk DB; Hwu WM
    IEEE Trans Parallel Distrib Syst; 2015 May; 26(5):1405-1418. PubMed ID: 26180487
    [TBL] [Abstract][Full Text] [Related]  

  • 10. Hardware-Software Partitioning for Real-Time Object Detection Using Dynamic Parameter Optimization.
    Zaharia C; Popescu V; Sandu F
    Sensors (Basel); 2023 May; 23(10):. PubMed ID: 37430806
    [TBL] [Abstract][Full Text] [Related]  

  • 11. Efficient Binary Weight Convolutional Network Accelerator for Speech Recognition.
    Guo L; Mu S; Deng Y; Shi C; Yan B; Xiao Z
    Sensors (Basel); 2023 Jan; 23(3):. PubMed ID: 36772567
    [TBL] [Abstract][Full Text] [Related]  

  • 12. EDSSA: An Encoder-Decoder Semantic Segmentation Networks Accelerator on OpenCL-Based FPGA Platform.
    Huang H; Wu Y; Yu M; Shi X; Qiao F; Luo L; Wei Q; Liu X
    Sensors (Basel); 2020 Jul; 20(14):. PubMed ID: 32708851
    [TBL] [Abstract][Full Text] [Related]  

  • 13. A hybrid short read mapping accelerator.
    Chen Y; Schmidt B; Maskell DL
    BMC Bioinformatics; 2013 Feb; 14():67. PubMed ID: 23441908
    [TBL] [Abstract][Full Text] [Related]  

  • 14. Acceleration of Deep Neural Network Training Using Field Programmable Gate Arrays.
    Tufa GT; Andargie FA; Bijalwan A
    Comput Intell Neurosci; 2022; 2022():8387364. PubMed ID: 36299439
    [TBL] [Abstract][Full Text] [Related]  

  • 15. Resources and Power Efficient FPGA Accelerators for Real-Time Image Classification.
    Kyriakos A; Papatheofanous EA; Bezaitis C; Reisis D
    J Imaging; 2022 Apr; 8(4):. PubMed ID: 35448240
    [TBL] [Abstract][Full Text] [Related]  

  • 16. Custom Hardware Architectures for Deep Learning on Portable Devices: A Review.
    Zaman KS; Reaz MBI; Md Ali SH; Bakar AAA; Chowdhury MEH
    IEEE Trans Neural Netw Learn Syst; 2022 Nov; 33(11):6068-6088. PubMed ID: 34086580
    [TBL] [Abstract][Full Text] [Related]  

  • 17. A Heterogeneous Hardware Accelerator for Image Classification in Embedded Systems.
    Pérez I; Figueroa M
    Sensors (Basel); 2021 Apr; 21(8):. PubMed ID: 33918668
    [TBL] [Abstract][Full Text] [Related]  

  • 18. FPGA-Based Feature Extraction and Tracking Accelerator for Real-Time Visual SLAM.
    Zhang J; Xiong S; Liu C; Geng Y; Xiong W; Cheng S; Hu F
    Sensors (Basel); 2023 Sep; 23(19):. PubMed ID: 37836865
    [TBL] [Abstract][Full Text] [Related]  

  • 19. Recurrent neural network FPGA hardware accelerator for delay-tolerant indoor optical wireless communications.
    Lee J; Song T; He J; Kandeepan S; Wang K
    Opt Express; 2021 Aug; 29(16):26165-26182. PubMed ID: 34614928
    [TBL] [Abstract][Full Text] [Related]  

  • 20. High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point.
    Fan H; Liu S; Que Z; Niu X; Luk W
    IEEE Trans Neural Netw Learn Syst; 2023 Aug; 34(8):4473-4487. PubMed ID: 34644253
    [TBL] [Abstract][Full Text] [Related]  

    [Next]    [New Search]
    of 6.