These tools will no longer be maintained as of December 31, 2024. Archived website can be found here. PubMed4Hh GitHub repository can be found here. Contact NLM Customer Service if you have questions.


BIOMARKERS

Molecular Biopsy of Human Tumors

- a resource for Precision Medicine *

157 related articles for article (PubMed ID: 36846531)

  • 1. Performance analysis of multiple input single layer neural network hardware chip.
    Goel A; Goel AK; Kumar A
    Multimed Tools Appl; 2023 Feb; ():1-22. PubMed ID: 36846531
    [TBL] [Abstract][Full Text] [Related]  

  • 2. DeepX: Deep Learning Accelerator for Restricted Boltzmann Machine Artificial Neural Networks.
    Kim LW
    IEEE Trans Neural Netw Learn Syst; 2018 May; 29(5):1441-1453. PubMed ID: 28287986
    [TBL] [Abstract][Full Text] [Related]  

  • 3. Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network.
    Shah N; Chaudhari P; Varghese K
    IEEE Trans Neural Netw Learn Syst; 2018 Dec; 29(12):5922-5934. PubMed ID: 29993989
    [TBL] [Abstract][Full Text] [Related]  

  • 4. A FPGA-Based, Granularity-Variable Neuromorphic Processor and Its Application in a MIMO Real-Time Control System.
    Zhang Z; Ma C; Zhu R
    Sensors (Basel); 2017 Aug; 17(9):. PubMed ID: 28832522
    [TBL] [Abstract][Full Text] [Related]  

  • 5. A System-on-Chip Based Hybrid Neuromorphic Compute Node Architecture for Reproducible Hyper-Real-Time Simulations of Spiking Neural Networks.
    Trensch G; Morrison A
    Front Neuroinform; 2022; 16():884033. PubMed ID: 35846779
    [TBL] [Abstract][Full Text] [Related]  

  • 6. Parallel fixed point implementation of a radial basis function network in an FPGA.
    de Souza AC; Fernandes MA
    Sensors (Basel); 2014 Sep; 14(10):18223-43. PubMed ID: 25268918
    [TBL] [Abstract][Full Text] [Related]  

  • 7. High-performance reconfigurable hardware architecture for restricted Boltzmann machines.
    Ly DL; Chow P
    IEEE Trans Neural Netw; 2010 Nov; 21(11):1780-92. PubMed ID: 20858578
    [TBL] [Abstract][Full Text] [Related]  

  • 8. Distributed large-scale graph processing on FPGAs.
    Sahebi A; Barbone M; Procaccini M; Luk W; Gaydadjiev G; Giorgi R
    J Big Data; 2023; 10(1):95. PubMed ID: 37283690
    [TBL] [Abstract][Full Text] [Related]  

  • 9. Sequential logic circuit gold codes for electronics and communication technologies.
    Devrari A; Kumar A; Kuchhal P; Illés Z; Verma C
    MethodsX; 2024 Jun; 12():102602. PubMed ID: 38379719
    [TBL] [Abstract][Full Text] [Related]  

  • 10. Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip.
    Perri S; Sestito C; Spagnolo F; Corsonello P
    J Imaging; 2020 Aug; 6(9):. PubMed ID: 34460742
    [TBL] [Abstract][Full Text] [Related]  

  • 11. FPGA Correlator for Applications in Embedded Smart Devices.
    Moore CH; Lin W
    Biosensors (Basel); 2022 Apr; 12(4):. PubMed ID: 35448296
    [TBL] [Abstract][Full Text] [Related]  

  • 12. Hardware Trojan Attacks on the Reconfigurable Interconnections of Field-Programmable Gate Array-Based Convolutional Neural Network Accelerators and a Physically Unclonable Function-Based Countermeasure Detection Technique.
    Hou J; Liu Z; Yang Z; Yang C
    Micromachines (Basel); 2024 Jan; 15(1):. PubMed ID: 38276848
    [TBL] [Abstract][Full Text] [Related]  

  • 13. A Scalable FPGA Architecture for Randomly Connected Networks of Hodgkin-Huxley Neurons.
    Akbarzadeh-Sherbaf K; Abdoli B; Safari S; Vahabie AH
    Front Neurosci; 2018; 12():698. PubMed ID: 30356803
    [TBL] [Abstract][Full Text] [Related]  

  • 14. Resources and Power Efficient FPGA Accelerators for Real-Time Image Classification.
    Kyriakos A; Papatheofanous EA; Bezaitis C; Reisis D
    J Imaging; 2022 Apr; 8(4):. PubMed ID: 35448240
    [TBL] [Abstract][Full Text] [Related]  

  • 15. NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors.
    Cheung K; Schultz SR; Luk W
    Front Neurosci; 2015; 9():516. PubMed ID: 26834542
    [TBL] [Abstract][Full Text] [Related]  

  • 16. SOMprocessor: A high throughput FPGA-based architecture for implementing Self-Organizing Maps and its application to video processing.
    Sousa MAA; Pires R; Del-Moral-Hernandez E
    Neural Netw; 2020 May; 125():349-362. PubMed ID: 32179330
    [TBL] [Abstract][Full Text] [Related]  

  • 17. Modular particle filtering FPGA hardware architecture for brain machine interfaces.
    Mountney J; Obeid I; Silage D
    Annu Int Conf IEEE Eng Med Biol Soc; 2011; 2011():4617-20. PubMed ID: 22255366
    [TBL] [Abstract][Full Text] [Related]  

  • 18. A Heterogeneous Hardware Accelerator for Image Classification in Embedded Systems.
    Pérez I; Figueroa M
    Sensors (Basel); 2021 Apr; 21(8):. PubMed ID: 33918668
    [TBL] [Abstract][Full Text] [Related]  

  • 19. Gas sensors characterization and multilayer perceptron (MLP) hardware implementation for gas identification using a Field Programmable Gate Array (FPGA).
    Benrekia F; Attari M; Bouhedda M
    Sensors (Basel); 2013 Mar; 13(3):2967-85. PubMed ID: 23529119
    [TBL] [Abstract][Full Text] [Related]  

  • 20. Adaptive cognition implemented with a context-aware and flexible neuron for next-generation artificial intelligence.
    Jadaun P; Cui C; Liu S; Incorvia JAC
    PNAS Nexus; 2022 Nov; 1(5):pgac206. PubMed ID: 36712357
    [TBL] [Abstract][Full Text] [Related]  

    [Next]    [New Search]
    of 8.