These tools will no longer be maintained as of December 31, 2024. Archived website can be found here. PubMed4Hh GitHub repository can be found here. Contact NLM Customer Service if you have questions.
124 related articles for article (PubMed ID: 37176997)
41. A Scalable Bidimensional Randomization Scheme for TLC 3D NAND Flash Memories. Favalli M; Zambelli C; Marelli A; Micheloni R; Olivo P Micromachines (Basel); 2021 Jun; 12(7):. PubMed ID: 34199140 [TBL] [Abstract][Full Text] [Related]
42. Prediction models of bit errors for NAND flash memory using 200 days of measured data. Wei D; Qiao L; Chen X; Feng H; Peng X Rev Sci Instrum; 2019 Jun; 90(6):064702. PubMed ID: 31255025 [TBL] [Abstract][Full Text] [Related]
43. A four-bit-per-cell program method with substrate-bias assisted hot electron injection for charge trap flash memory devices. An HM; Kim HD; Kim B; Kim TG J Nanosci Nanotechnol; 2013 May; 13(5):3293-7. PubMed ID: 23858846 [TBL] [Abstract][Full Text] [Related]
44. Interface engineering of 9X stacked 3D NAND flash memory using hydrogen post-treatment annealing. Choi S; Kim S; Bang S; Kim J; Park DG; Jin S; Kim MJ; Kwon E; Lee JW Nanotechnology; 2022 Oct; 34(2):. PubMed ID: 36198255 [TBL] [Abstract][Full Text] [Related]
45. Investigation of the Connection Schemes between Decks in 3D NAND Flash. Jia J; Jin L; You K; Zhu A Micromachines (Basel); 2023 Sep; 14(9):. PubMed ID: 37763942 [TBL] [Abstract][Full Text] [Related]
46. Future prospects of NAND flash memory technology--the evolution from floating gate to charge trapping to 3D stacking. Lu CY J Nanosci Nanotechnol; 2012 Oct; 12(10):7604-18. PubMed ID: 23421122 [TBL] [Abstract][Full Text] [Related]
47. Threshold voltage instability mechanisms of nitride based charge trap flash memory--a review. Lee MC; Wong HY J Nanosci Nanotechnol; 2014 Jul; 14(7):4799-812. PubMed ID: 24757947 [TBL] [Abstract][Full Text] [Related]
48. Dielectric-Engineered High-Speed, Low-Power, Highly Reliable Charge Trap Flash-Based Synaptic Device for Neuromorphic Computing beyond Inference. Kim JP; Kim SK; Park S; Kuk SH; Kim T; Kim BH; Ahn SH; Cho YH; Jeong Y; Choi SY; Kim S Nano Lett; 2023 Jan; 23(2):451-461. PubMed ID: 36637103 [TBL] [Abstract][Full Text] [Related]
49. Compression-Assisted Adaptive ECC and RAID Scattering for NAND Flash Storage Devices. Lim SH; Park KW Sensors (Basel); 2020 May; 20(10):. PubMed ID: 32456045 [TBL] [Abstract][Full Text] [Related]
50. Paving the Way for Pass Disturb-Free Vertical NAND Storage via a Dedicated and String-Compatible Pass Gate. Zhao Z; Woo S; Aabrar KA; Kirtania SG; Jiang Z; Deng S; Xiao Y; Mulaosmanovic H; Duenkel S; Kleimaier D; Soss S; Beyer S; Joshi R; Meninger S; Mohamed M; Kim K; Woo J; Lim S; Kim K; Kim W; Ha D; Narayanan V; Datta S; Yu S; Ni K ACS Appl Mater Interfaces; 2024 Oct; ():. PubMed ID: 39374172 [TBL] [Abstract][Full Text] [Related]
51. Investigation of Intra-Nitride Charge Migration Suppression in SONOS Flash Memory. Yang SD; Jung JK; Lim JG; Park SG; Lee HD; Lee GW Micromachines (Basel); 2019 May; 10(6):. PubMed ID: 31146426 [TBL] [Abstract][Full Text] [Related]
52. Charge Trapping in Amorphous Dielectrics for Secure Charge Storage. Baik SJ; Shin H ACS Appl Mater Interfaces; 2021 Mar; 13(9):11507-11514. PubMed ID: 33621041 [TBL] [Abstract][Full Text] [Related]
53. An SVM-Based NAND Flash Endurance Prediction Method. Zhang H; Wang J; Chen Z; Pan Y; Lu Z; Liu Z Micromachines (Basel); 2021 Jun; 12(7):. PubMed ID: 34202062 [TBL] [Abstract][Full Text] [Related]
54. Effect of Word-Line Bias on Linearity of Multi-Level Conductance Steps for Multi-Layer Neural Networks Based on NAND Flash Cells. Lee ST; Lim S; Choi N; Bae JH; Kwon D; Kim HS; Park BG; Lee JH J Nanosci Nanotechnol; 2020 Jul; 20(7):4138-4142. PubMed ID: 31968431 [TBL] [Abstract][Full Text] [Related]
55. Two-bit memory and quantized storage phenomenon in conventional MOS structures with double-stacked Pt-NCs in an HfAlO matrix. Zhou G; Wu B; Liu X; Li P; Zhang S; Sun B; Zhou A Phys Chem Chem Phys; 2016 Mar; 18(9):6509-14. PubMed ID: 26864686 [TBL] [Abstract][Full Text] [Related]
56. Effect of adjacent bit-line cell interference on low frequency noise in NAND flash memory cell strings. Jo BS; Joe SM; Jeong MK; Han KR; Park SK; Lee JH J Nanosci Nanotechnol; 2013 Sep; 13(9):6405-8. PubMed ID: 24205670 [TBL] [Abstract][Full Text] [Related]
57. Understanding the Origin of Metal Gate Work Function Shift and Its Impact on Erase Performance in 3D NAND Flash Memories. Ramesh S; Ajaykumar A; Ragnarsson LÅ; Breuil L; El Hajjam GK; Kaczer B; Belmonte A; Nyns L; Soulié JP; Van den Bosch G; Rosmeulen M Micromachines (Basel); 2021 Sep; 12(9):. PubMed ID: 34577727 [TBL] [Abstract][Full Text] [Related]
58. Controlling the Carrier Injection Efficiency in 3D Nanocrystalline Silicon Floating Gate Memory by Novel Design of Control Layer. Hu H; Ma Z; Yu X; Chen T; Zhou C; Li W; Chen K; Xu J; Xu L Nanomaterials (Basel); 2023 Mar; 13(6):. PubMed ID: 36985856 [TBL] [Abstract][Full Text] [Related]
60. Retention Enhancement in Low Power NOR Flash Array with High-κ-Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide. Song YS; Park BG Micromachines (Basel); 2021 Mar; 12(3):. PubMed ID: 33808915 [TBL] [Abstract][Full Text] [Related] [Previous] [Next] [New Search]