These tools will no longer be maintained as of December 31, 2024. Archived website can be found here. PubMed4Hh GitHub repository can be found here. Contact NLM Customer Service if you have questions.


BIOMARKERS

Molecular Biopsy of Human Tumors

- a resource for Precision Medicine *

118 related articles for article (PubMed ID: 38675261)

  • 1. High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNIC.
    Song X; Lu R; Guo Z
    Micromachines (Basel); 2024 Mar; 15(4):. PubMed ID: 38675261
    [TBL] [Abstract][Full Text] [Related]  

  • 2. The Design of a Dynamic Configurable Packet Parser Based on FPGA.
    Sun Y; Guo Z
    Micromachines (Basel); 2023 Aug; 14(8):. PubMed ID: 37630096
    [TBL] [Abstract][Full Text] [Related]  

  • 3. An FPGA-Based ECU for Remote Reconfiguration in Automotive Systems.
    Cho K; Kim J; Choi DY; Yoon YH; Oh JH; Lee SE
    Micromachines (Basel); 2021 Oct; 12(11):. PubMed ID: 34832721
    [TBL] [Abstract][Full Text] [Related]  

  • 4. Peptide mass fingerprinting using field-programmable gate arrays.
    Bogdan IA; Coca D; Beynon RJ
    IEEE Trans Biomed Circuits Syst; 2009 Jun; 3(3):142-9. PubMed ID: 23853215
    [TBL] [Abstract][Full Text] [Related]  

  • 5. Hardware Trojan Attacks on the Reconfigurable Interconnections of Field-Programmable Gate Array-Based Convolutional Neural Network Accelerators and a Physically Unclonable Function-Based Countermeasure Detection Technique.
    Hou J; Liu Z; Yang Z; Yang C
    Micromachines (Basel); 2024 Jan; 15(1):. PubMed ID: 38276848
    [TBL] [Abstract][Full Text] [Related]  

  • 6. Dynamically Reconfigurable Encryption and Decryption System Design for the Internet of Things Information Security.
    Wang Z; Yao Y; Tong X; Luo Q; Chen X
    Sensors (Basel); 2019 Jan; 19(1):. PubMed ID: 30609820
    [TBL] [Abstract][Full Text] [Related]  

  • 7. Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications.
    Ijaz Q; Kidane HL; Bourennane EB; Ochoa-Ruiz G
    Micromachines (Basel); 2023 Oct; 14(10):. PubMed ID: 37893350
    [TBL] [Abstract][Full Text] [Related]  

  • 8. SHA-256 Hardware Proposal for IoT Devices in the Blockchain Context.
    Santos CEB; Silva LMDD; Torquato MF; Silva SN; Fernandes MAC
    Sensors (Basel); 2024 Jun; 24(12):. PubMed ID: 38931692
    [TBL] [Abstract][Full Text] [Related]  

  • 9. Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network.
    Shah N; Chaudhari P; Varghese K
    IEEE Trans Neural Netw Learn Syst; 2018 Dec; 29(12):5922-5934. PubMed ID: 29993989
    [TBL] [Abstract][Full Text] [Related]  

  • 10. FPGA-Based Implementation of Multidimensional Reconciliation Encoding in Quantum Key Distribution.
    Lu Q; Lu Z; Yang H; Yang S; Li Y
    Entropy (Basel); 2022 Dec; 25(1):. PubMed ID: 36673221
    [TBL] [Abstract][Full Text] [Related]  

  • 11. A High-Performance and Flexible Architecture for Accelerating SDN on the MPSoC Platform.
    Sha M; Guo Z; Guo Y; Zeng X
    Micromachines (Basel); 2022 Oct; 13(11):. PubMed ID: 36363875
    [TBL] [Abstract][Full Text] [Related]  

  • 12. Hardware Implementations of a Deep Learning Approach to Optimal Configuration of Reconfigurable Intelligence Surfaces.
    Martín-Martín A; Padial-Allué R; Castillo E; Parrilla L; Parellada-Serrano I; Morán A; García A
    Sensors (Basel); 2024 Jan; 24(3):. PubMed ID: 38339618
    [TBL] [Abstract][Full Text] [Related]  

  • 13. Investigation on Vision System: Digital FPGA Implementation in Case of Retina Rod Cells.
    Ghanbarpour M; Haghiri S; Hazzazi F; Assaad M; Chaudhary MA; Ahmadi A
    IEEE Trans Biomed Circuits Syst; 2024 Apr; 18(2):299-307. PubMed ID: 37824307
    [TBL] [Abstract][Full Text] [Related]  

  • 14. Design and implementation of an FPGA-based timing pulse programmer for pulsed-electron paramagnetic resonance applications.
    Sun L; Savory JJ; Warncke K
    Concepts Magn Reson Part B Magn Reson Eng; 2013 Aug; 43(3):100-109. PubMed ID: 25076864
    [TBL] [Abstract][Full Text] [Related]  

  • 15. Cost-Effective Network Reordering Using FPGA.
    Hoang VQ; Chen Y
    Sensors (Basel); 2023 Jan; 23(2):. PubMed ID: 36679615
    [TBL] [Abstract][Full Text] [Related]  

  • 16. On the dynamic reconfigurable implementations of MISTY1 and KASUMI block ciphers.
    Jiexian H; Khizar Y; Ali ZA; Hasan R; Pathan MS
    PLoS One; 2023; 18(9):e0291429. PubMed ID: 37768962
    [TBL] [Abstract][Full Text] [Related]  

  • 17. An FPGA Platform for Real-Time Simulation of Spiking Neuronal Networks.
    Pani D; Meloni P; Tuveri G; Palumbo F; Massobrio P; Raffo L
    Front Neurosci; 2017; 11():90. PubMed ID: 28293163
    [TBL] [Abstract][Full Text] [Related]  

  • 18. A Model-Driven Platform for Dynamic Partially Reconfigurable Architectures: A Case Study of a Watermarking System.
    Dalbouchi R; Trabelsi C; Elhajji M; Zitouni A
    Micromachines (Basel); 2023 Feb; 14(2):. PubMed ID: 36838181
    [TBL] [Abstract][Full Text] [Related]  

  • 19. Resources and Power Efficient FPGA Accelerators for Real-Time Image Classification.
    Kyriakos A; Papatheofanous EA; Bezaitis C; Reisis D
    J Imaging; 2022 Apr; 8(4):. PubMed ID: 35448240
    [TBL] [Abstract][Full Text] [Related]  

  • 20. High throughput resource efficient reconfigurable interleaver for MIMO WLAN application.
    Upadhyaya BK; Pramanik PKD; Sanyal SK
    PeerJ Comput Sci; 2021; 7():e581. PubMed ID: 34179450
    [TBL] [Abstract][Full Text] [Related]  

    [Next]    [New Search]
    of 6.