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Title: A front-end automation tool supporting design, verification and reuse of SOC. Author: Yan XL, Yu LL, Wang JB. Journal: J Zhejiang Univ Sci; 2004 Sep; 5(9):1102-5. PubMed ID: 15323005. Abstract: This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.[Abstract] [Full Text] [Related] [New Search]