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  • Title: Key integration technologies for nanoscale FRAMs.
    Author: Jung DJ, Kim HH, Kim K.
    Journal: IEEE Trans Ultrason Ferroelectr Freq Control; 2007 Dec; 54(12):2535-40. PubMed ID: 18276551.
    Abstract:
    We discuss key technologies of 180-nm node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with metal-insulator-metal (MIM) capacitors. The key integration technologies in ferroelectric random access memory (FRAM) comprise: etching technology to have less plasma damage; stack technology for the preparation of robust ferroelectrics; capping technology to encapsulate cell capacitors; and vertical conjunction technology to connect cell capacitors to the plate line. What has been achieved from these novel approaches is not only to have a peak-to-peak value of 675 mV in bit-line potential but also to ensure a sensing margin of 300 mV in opposite-state retention, even after 1000 hour suffering at 150 degrees C.
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