These tools will no longer be maintained as of December 31, 2024. Archived website can be found here. PubMed4Hh GitHub repository can be found here. Contact NLM Customer Service if you have questions.


Pubmed for Handhelds

PUBMED FOR HANDHELDS

Journal Abstract Search

484 related items for PubMed ID: 22552118

  • 1. Few electron limit of n-type metal oxide semiconductor single electron transistors.
    Prati E, De Michielis M, Belli M, Cocco S, Fanciulli M, Kotekar-Patil D, Ruoff M, Kern DP, Wharam DA, Verduijn J, Tettamanzi GC, Rogge S, Roche B, Wacquez R, Jehl X, Vinet M, Sanquer M.
    Nanotechnology; 2012 Jun 01; 23(21):215204. PubMed ID: 22552118
    [Abstract] [Full Text] [Related]

  • 2. Channel length scaling of MoS2 MOSFETs.
    Liu H, Neal AT, Ye PD.
    ACS Nano; 2012 Oct 23; 6(10):8563-9. PubMed ID: 22957650
    [Abstract] [Full Text] [Related]

  • 3. Fabrication of poly-silicon nano-wire transistors on plastic substrates.
    Park C, Lee S, Choi M, Kang M, Jung Y, Hwang S, Ahn D, Lee J, Song C.
    J Nanosci Nanotechnol; 2007 Nov 23; 7(11):4150-3. PubMed ID: 18047139
    [Abstract] [Full Text] [Related]

  • 4. Realization of a silicon nanowire vertical surround-gate field-effect transistor.
    Schmidt V, Riel H, Senz S, Karg S, Riess W, Gösele U.
    Small; 2006 Jan 23; 2(1):85-8. PubMed ID: 17193560
    [No Abstract] [Full Text] [Related]

  • 5. Optimized structural designs for stretchable silicon integrated circuits.
    Kim DH, Liu Z, Kim YS, Wu J, Song J, Kim HS, Huang Y, Hwang KC, Zhang Y, Rogers JA.
    Small; 2009 Dec 23; 5(24):2841-7. PubMed ID: 19824002
    [Abstract] [Full Text] [Related]

  • 6. n-Type behavior of graphene supported on Si/SiO(2) substrates.
    Romero HE, Shen N, Joshi P, Gutierrez HR, Tadigadapa SA, Sofo JO, Eklund PC.
    ACS Nano; 2008 Oct 28; 2(10):2037-44. PubMed ID: 19206449
    [Abstract] [Full Text] [Related]

  • 7. Negative differential resistance in carbon nanotube field-effect transistors with patterned gate oxide.
    Rinkiö M, Johansson A, Kotimäki V, Törmä P.
    ACS Nano; 2010 Jun 22; 4(6):3356-62. PubMed ID: 20524681
    [Abstract] [Full Text] [Related]

  • 8. Metal-insulator-silicon-insulator-metal waveguides compatible with standard CMOS technology.
    Kwon MS.
    Opt Express; 2011 Apr 25; 19(9):8379-93. PubMed ID: 21643089
    [Abstract] [Full Text] [Related]

  • 9. CMOS-compatible fabrication of room-temperature single-electron devices.
    Ray V, Subramanian R, Bhadrachalam P, Ma LC, Kim CU, Koh SJ.
    Nat Nanotechnol; 2008 Oct 25; 3(10):603-8. PubMed ID: 18838999
    [Abstract] [Full Text] [Related]

  • 10. Reconfigurable silicon nanowire transistors.
    Heinzig A, Slesazeck S, Kreupl F, Mikolajick T, Weber WM.
    Nano Lett; 2012 Jan 11; 12(1):119-24. PubMed ID: 22111808
    [Abstract] [Full Text] [Related]

  • 11. Three-dimensional etching of silicon for the fabrication of low-dimensional and suspended devices.
    Walavalkar SS, Homyk AP, Henry MD, Scherer A.
    Nanoscale; 2013 Feb 07; 5(3):927-31. PubMed ID: 23292113
    [Abstract] [Full Text] [Related]

  • 12. A novel method for fabricating sub-16 nm footprint T-gate nanoimprint molds.
    Peng C, Liang X, Chou SY.
    Nanotechnology; 2009 May 06; 20(18):185302. PubMed ID: 19420609
    [Abstract] [Full Text] [Related]

  • 13. Enhanced electroluminescence from nanoscale silicon p+ -n junctions made with an anodic aluminum oxide pattern.
    Hong T, Chen T, Ran GZ, Wen J, Li YZ, Dai T, Qin GG.
    Nanotechnology; 2010 Jan 15; 21(2):025301. PubMed ID: 19955614
    [Abstract] [Full Text] [Related]

  • 14. Integrated circuits and logic operations based on single-layer MoS2.
    Radisavljevic B, Whitwick MB, Kis A.
    ACS Nano; 2011 Dec 27; 5(12):9934-8. PubMed ID: 22073905
    [Abstract] [Full Text] [Related]

  • 15. Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.
    Sun MC, Kim G, Kim SW, Kim HW, Kim H, Lee JH, Shin H, Park BG.
    J Nanosci Nanotechnol; 2012 Jul 27; 12(7):5313-7. PubMed ID: 22966563
    [Abstract] [Full Text] [Related]

  • 16. Fabrication of ultrathin and highly uniform silicon on insulator by numerically controlled plasma chemical vaporization machining.
    Sano Y, Yamamura K, Mimura H, Yamauchi K, Mori Y.
    Rev Sci Instrum; 2007 Aug 27; 78(8):086102. PubMed ID: 17764362
    [Abstract] [Full Text] [Related]

  • 17. Porphyrin-silicon hybrid field-effect transistor with individually addressable top-gate structure.
    Seol ML, Choi SJ, Kim CH, Moon DI, Choi YK.
    ACS Nano; 2012 Jan 24; 6(1):183-9. PubMed ID: 22148941
    [Abstract] [Full Text] [Related]

  • 18. Quantum mechanical device modeling: FinFET having an isolated n+/p+ gate region strapped with poly-silicon.
    Kim HG, Kim JS, Kim YK, Won T.
    J Nanosci Nanotechnol; 2007 Nov 24; 7(11):4135-8. PubMed ID: 18047135
    [Abstract] [Full Text] [Related]

  • 19. Transport characteristics of multichannel transistors made from densely aligned sub-10 nm half-pitch graphene nanoribbons.
    Liang X, Wi S.
    ACS Nano; 2012 Nov 27; 6(11):9700-10. PubMed ID: 23078122
    [Abstract] [Full Text] [Related]

  • 20. Morphological impact of zinc oxide layers on the device performance in thin-film transistors.
    Faber H, Klaumünzer M, Voigt M, Galli D, Vieweg BF, Peukert W, Spiecker E, Halik M.
    Nanoscale; 2011 Mar 27; 3(3):897-9. PubMed ID: 21116548
    [Abstract] [Full Text] [Related]

    Page: [Next] [New Search]
    of 25.